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We are professional, agile, and our goal is to We are professional, innovative, agile, and our goal is to We are innovative, professional, and our goal is to AI Atlas Inc: Innovative optical transceiver technology provider with smart DSP chips and real-time monitoring capabilities...

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Job Description: We are looking for Postdoc or senior PhD, who is knowledgeable on Xilinx Zynq SoC type of FPGAs, with experience on Xilinx Ultrascale+ RFSoC being a strong plus. The ideal candidate should specialize in FPGA infrastructure IP, including PCIe, interrupts, AXI Chip2Chip and AXI interconnect. Also, the candidate should have experience with FPGA interfaces, such as ADCs, DACs, DDR3 memory, UART, SPI, I2C, Aurora high-speed serial, PCI express Gen3 and Gen4, SFP28 ports, and GTY ports. The candidate should also have experience with design simulation using SystemVerilog and UVM, as well as Simulink and System Generator for DSP design, High-Level Synthesis, and Partial Reconfiguration.

Responsibilities:

• Develop and design FPGA hardware and firmware solutions.

• Collaborate with cross-functional teams to develop FPGA solutions for embedded systems.

• Create FPGA infrastructure IP and interface with third-party IP.

• Develop design simulations with SystemVerilog and UVM.

• Use Simulink and System Generator for DSP design.

• Utilize High-Level Synthesis and Partial Reconfiguration for efficient FPGA design.

• Utilize Matlab and C/C++ to convert m-file codes to HDL coder or system generator block and HLS.

• Use Vivado to program the FPGA.

• Perform hardware/software cosimulation to verify system functionality.

• Develop and maintain design documentation and specifications.

• Stay up-to-date with the latest industry trends and technologies related to FPGAs.

Good to have:

• Minimum of a master's degree in Electrical/Computer Engineering or related field.

• Strong knowledge of Xilinx Zynq SoC type of FPGAs.

• Experience with Xilinx Ultrascale+ RFSoC is a plus.

• Strong expertise in FPGA infrastructure IP, including PCIe, interrupts, AXI Chip2Chip and AXI interconnect.

• Familiarity with FPGA interfaces, such as ADCs, DACs, DDR3 memory, UART, SPI, I2C, Aurora high-speed serial, PCI express Gen3 and Gen4, SFP28 ports, and GTY ports.

• Experience with design simulation using SystemVerilog and UVM.

• Familiarity with Simulink and System Generator for DSP design, High-Level Synthesis, and Partial Reconfiguration.

• Ability to convert m-file codes to HDL coder or system generator block and HLS.

• Experience with Vivado to program the FPGA.

• Experience with hardware/software cosimulation.

• Proficient in Matlab and C/C++.

• Excellent problem-solving and analytical skills.

• Strong attention to detail and ability to work independently and as part of a team.

• Excellent communication and interpersonal skills.

About the hiring University:

• McMaster University is a public research university in Hamilton, Ontario, Canada. The main McMaster campus is on 121 hectares of land near the residential neighbourhoods of Ainslie Wood and Westdale, adjacent to the Royal Botanical Gardens.

• McMaster is Canada's most research-intensive university (awarded four years in a row), one of the top 80 universities in the world, #4 in Canada, and ranked #17 in the world for global impact

• McMaster is committed to advancing human and societal health and well-being, creating a better world through collaborative learning, fostering increased creativity through cross-faculty dialogue, supporting innovative thinking, and striving for global impact with an inclusive mindset

• The engineering department has expert supervising Professors in this exact field of study

• McMaster university is working in conjunction with AI Atlas Inc.

Job Types: Full-time, Fixed term contract

Contract length: 12 months

Benefits:

• Dental care

• Paid time off

Flexible Language Requirement:

• French not required

Schedule:

• Monday to Friday

Education:

• Doctoral Degree (preferred)

Language:

• English (required)

Willingness to travel:

• 25% (preferred)

Work Location: Remote